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TB6560AHQ/AFG
TOSHIBA BiCD Integrated Circuit Silicon Monolithic
TB6560AHQ,TB6560AFG
PWM Chopper-Type Bipolar Driver IC for Stepping Motor Control
The TB6560AHQ/AFG is a PWM chopper-type stepping motor driver IC designed for sinusoidal-input microstep control of bipolar stepping motors. The TB6560AHQ/AFG can be used in applications that require 2-phase, 1-2-phase, 2W1-2-phase and 4W1-2-phase excitation modes. The TB6560AHQ/AFG is capable of low-vibration, high-performance forward and reverse driving of a two-phase bipolar stepping motor using only a clock signal.
TB6560AHQ
Features
* * * * * * * * * * * Single-chip motor driver for sinusoidal microstep control of stepping motors High output withstand voltage due to the use of BiCD process: Ron (upper and lower sum) = 0.6 (typ.) Forward and reverse rotation Selectable phase excitation modes (2, 1-2, 2W1-2 and 4W1-2) High output withstand voltage: VDSS = 40 V High output current: IOUT = AHQ: 3.5 A (peak) AFG: 2.5 A (peak) Packages: HZIP25-P-1.27/HQFP64-P-1010-0.50 Internal pull-down resistors on inputs: 100 k (typ.) Output monitor pin: MO current (IMO (max) = 1 mA) Reset and enable pins Thermal shutdown (TSD) The TB6560AFG is RoHS compatible. The TB6560AHQ is a Sn-plated product. (The Pb-containing materials with a high melting point that are exempted from RoHS directives are used inside the IC.) The following conditions apply to solderability: *Solderability 1. Use of Sn-37Pb solder bath *solder bath temperature = 230C *dipping time = 5 seconds *number of times = once *use of R-type flux 2. Use of Sn-3.0Ag-0.5Cu solder bath *solder bath temperature = 245C *dipping time = 5 seconds *the number of times = once Weight: HZIP25-P-1.27: 9.86 g (typ.) HQFP64-P-1010-0.50: 0.26 g (typ.)
TB6560AFG
*: These ICs are highly sensitive to electrostatic discharge. When handling them, ensure that the environment is protected against electrostatic discharge. Ensure also that the ambient temperature and relative humidity are maintained at reasonable level.
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Block Diagram
VDD 20/30, 31 M1 23/36
Protect 19/28
MO 17/23 Decoder
VMA 18/25, 26 OUT_AP 16/19, 20 Bridge driver A 13/10, 11
M2 22/35
CW/CCW 21/33
Thermal shutdown circuit
OUT_AM NFA
CLK
3/45 Input circuit
14/13, 14
RESET 5/48
Current selector circuit A
+ 8/55, 56 VMB OUT_BP
ENABLE
4/47
DCY1 25/39 Decoder DCY2 24/38 Bridge driver B
12/6, 7
9/61, 62 OSC 7/53 OSC Current selector circuit B Maximum current setting circuit 2/43 TQ1 1/42 TQ2 SGND PGNDA PGNDB 6/50, 51 15/16 10/64 + OUT_BM NFB
11/2, 4
TB6560AHQ/TB6560AFG
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Pin Functions
Pin No. AHQ 1 2 3 4 5 AFG 42 43 45 47 48 I/O Input Input Input Input Input Symbol TQ2 TQ1 CLK ENABLE Functional Description Torque setting input (current setting) Torque setting input (current setting) Clock input for microstepping H: Enable; L: All outputs OFF Remarks Internal pull-down resistor Internal pull-down resistor Internal pull-down resistor Internal pull-down resistor
RESET SGND OSC VMB OUT_BM PGNDB NFB OUT_BP OUT_AM NFA PGNDA OUT_AP MO VMA Protect VDD CW/CCW M2 M1 DCY2 DCY1
L: Reset (The outputs are reset to their initial states.) Signal ground (for control block) A CR oscillation circuit is connected to this pin. Performs output chopping. Motor power supply pin (for phase-B driver) OUT_B output Power ground Connection pin for a B-channel current sensing resistor Two pins of the TB6560AFG should be short-circuited. OUT_B output OUT_A output Connection pin for a A-channel current sensing resistor Two pins of the TB6560AFG should be short-circuited. Power ground OUT_A output Initial state sensing output. This pin is enabled in the initial state. Motor power supply pin (for phase-A driver) When TSD is activated: High; when in normal state: High-Z. Power supply pin for control block Rotation direction select input. L: Clockwise; H: Counterclockwise Excitation mode setting input Excitation mode setting input Current decay mode setting input Current decay mode setting input
Internal pull-down resistor (Note 1)
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
50/51 53 55/56 61/62 64 (*) 2/4 (*) 6/7 10/11 13/14 (*) 16 19/20 23 25/26 28 30/31 33 35 36 38 39
Input Output

(Note 1) (Note 1)
(Note 1) (Note 1) (Note 1) (Note 1)
Output Output

Output Output Input Output Input Input Input Input Input Input
(Note 1) Open drain (Note 1) Open drain (Note 1) Internal pull-down resistor Internal pull-down resistor Internal pull-down resistor Internal pull-down resistor Internal pull-down resistor
(*) : The pin assignment of the TB6560AFG is different from that of the TB6560FG. TB6560AHQ: There is no no-connect (NC) pin. TB6560AFG: Except the above pins, all pins are NC. The pin numbers of NC pins are: 1, 3, 5, 8, 9, 12, 15, 17, 18, 21, 22, 24, 27, 29, 32, 34, 37, 40, 41, 44, 46, 49, 52, 54, 57, 58, 59, 60, and 63. Applying a voltage to NC pins does not cause any problem since they are not connected inside the IC. All control input pins have an internal pull-down resistor of 100 k (typ.) Note 1: As for the TB6560AFG, two pins that have the same functionality should be short-circuited at a location as close to the TB6560AFG as possible. (The electrical characteristics provided in this document are measured when those pins are handled in this manner.)
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Equivalent Circuits
Input Pins (M1, M2, CLK, CW/CCW, ENABLE and RESET ) VDD 100 100
100 k
Output Pins (MO, Protect)
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Pin Assignment (top view)
TB6560AFG
CW/CCW ENABLE RESET
DCY1
DCY2
(NC)
(NC)
(NC)
(NC)
(NC)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
(NC)
CLK
TQ1
TQ2
M1
M2
33
(NC) SGND SGND (NC)
49 50 51 52
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
(NC) VDD VDD (NC) Protect (NC) VMA VMA (NC) MO (NC) (NC) OUT_AP OUT_AP (NC) (NC)
OSC 53 (NC) VMB VMB (NC) (NC) (NC) (NC) OUT_BM OUT_BM (NC) PGNDB 54 55 56 57 58 59 60 61 62 63 64
1
(NC)
2
NFB
3
(NC)
4
NFB
5
(NC)
6
OUT_BP
7
OUT_BP
8
(NC)
9
(NC)
10
OUT_AM
11
OUT_AM
12
(NC)
13
NFA
14
NFA
15
(NC) M2
16
PGNDA
TB6560AHQ
OUT_BP OUT_AP ENABLE SGND PGNDB DCY2
VMB
VMA
TQ1
2
4
6
8
10
12
NFA
14
16
18
VDD
20
22
24
1
TQ2
3
CLK
5
RESET
7
OSC
9
OUT_BM
11
NFB
13
OUT_AM
15
PGNDA
17
MO
19
Protect
21
CW/CCW
23
M1
25
DCY1
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Absolute Maximum Ratings (Ta = 25C)
Characteristics Power supply voltage AHQ AFG Symbol VDD VMA/B IO (PEAK) I (MO) VIN AHQ Power dissipation AFG Operating temperature Storage temperature Topr Tstg PD Rating 6 40 3.5 2.5 1 5.5 5 (Note 1) 43 (Note 2) 1.7 (Note 3) 4.2 (Note 4)
-30 to 85 -55 to 150
Unit V
Output current MO drain current Input voltage
Peak
A/phase mA V
W
C C
Note 1: Ta = 25C, without heatsink. Note 2: Ta = 25C, with infinite heatsink (HZIP25). Note 3: Ta = 25C, with soldered leads. Note 4: Ta = 25C, when mounted on a board (4-layer board).
Operating Range (Ta = -30 to 85C)
Characteristics Power supply voltage AHQ AFG Symbol VDD VMA/B IOUT VIN fCLK fOSC VMA/B VDD
Test Condition
Min 4.5 4.5

Typ. 5.0

Max 5.5 34 3 1.5 5.5 15 600
Unit V V A V kHz kHz
Output current Input voltage Clock frequency OSC frequency

0

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Electrical Characteristics (Ta = 25C, VDD = 5 V, VM = 24 V)
Characteristics Input voltage Input hysteresis voltage High Low (Note) Symbol VIN (H) VIN (L) VH IIN (H) IIN (L) IDD1 M1, M2, CW/CCW, CLK, RESET , ENABLE, DECAY, TQ1, TQ2, ISD VIN = 5.0 V Internal pull-down resistor VIN = 0 V Outputs: Open, RESET : H, ENABLE: H (2, 1-2 phase excitation) Outputs: Open, RESET : H, ENABLE: H (W1-2, 2W1-2 phase excitation) RESET : L, ENABLE: L M1, M2, CW/CCW, CLK, RESET , ENABLE, DECAY, TQ1, TQ2, ISD Test Condition Min 2.0
-0.2
Typ.

Max VDD 0.8
Unit V mV
400
Input current
30

55
80
A
1 5
3
VDD supply current
IDD2 IDD3 IDD4
-5
3 2 2 0.5 0.7
5 5 5 1 2 5 30 55 80 100
mA
RESET : H, ENABLE: L
RESET : H/L, ENABLE: L
VM supply current Channel-to-channel voltage differential
IM1 IM2
VO
RESET : H/L, ENABLE: H
B/A, COSC = 330 F TQ1 = H, TQ2 = H TQ1 = L, TQ2 = H TQ1 = H, TQ2 = L TQ1 = L, TQ2 = L C = 330 pF IOL = 1 mA

mA %
VNFHH VNF voltage change according to the torque settings VNFHL VNFLH VNFLL Minimum clock pulse width MO output residual voltage TSD threshold TSD hysteresis Oscillating frequency (Note) (Note) tW (CLK) VOL MO TSD TSDhys fOSC
10 47 70
20 50 75
%
30

s
0.5

V C C kHz
170 20 130
COSC = 330 pF
60
200
Note: Not tested in production
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Electrical Characteristics (Ta = 25C, VDD = 5 V, VM = 24 V)
Characteristics AHQ Output ON-resistance AFG 2W1-2phase excitation
Symbol Ron U1H Ron L1H Ron U1F Ron L1F
Test Condition IOUT = 1.5 A
Min

Typ. 0.3 0.3 0.35 0.35 100 100 98 96 92 88 83 77 71 63 56 47 38 29 20 10 100 500 1 1 1 3 2

Max 0.4 0.4 0.5 0.5

Unit
IOUT = 1.5 A
1-2phase excitation

=0 = 1/16 = 2/16 = 3/16 = 4/16 = 5/16 = 6/16 = 7/16
2W1-2phase excitation
93 91 87 83 78 72 TQ1 = L, TQ2 = L 66 58 51 42 33 24 15 5
100 100 97 93 88 82 % 76 68 61 52 43 34 25 15
2W1-2phase excitation
A-/B-phase chopping current (Note 1)
2W1-2phase excitation 4W1-2phase excitation
2W1-2phase excitation
1-2phase excitation

Vector
= 8/16 = 9/16 = 10/16 = 11/16 = 12/16 = 13/16 = 14/16 = 15/16
2W1-2phase excitation
2W1-2phase excitation
2W1-2phase excitation
2-phase excitation Reference voltage Output transistor switching characteristics VNF tr (Note 2) tf tpLH Delay time (Note 2) tpLH tpHL Output leakage current Upper side Lower side ILH ILL
TQ1, TQ2 = L (100%) OSC = 100 kHz RL = 10 , VNF = 0.5 V
450

550

mV
RESET to output
ENABLE to output
s
VM = 40 V
1 1
A
Note 1: Relative to the peak current at = 0. Note 2: Not tested in production.
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Functional Descriptions
1. Excitation Mode Settings
The excitation mode can be selected from the following four modes using the M1 and M2 inputs. (The 2-phase excitation mode is selected by default since both M1 and M2 have internal pull-down resistors.)
Inputs M2 L L H H M1 L H L H Mode (Excitation) 2-phase 1-2-phase 4W1-2-phase 2W1-2-phase
2. Function Table (Relationship Between Inputs and Output Modes)
When the ENABLE pin is Low, outputs are off. When the RESET pin is Low, the outputs are put in the Initial mode as shown in the table below. In this mode, the states of the CLK and CW/CCW pins are don't-cares.
Inputs CLK CW/CCW L H X X X X
RESET
H H L X
ENABLE H H H L CW
Output Mode
CCW Initial mode Z
X: Don't care
3. Initial Mode
When RESET is asserted, phase currents in each excitation mode are as follows. At this time, the MO pin goes Low (open-drain connection).
Excitation Mode 2-phase 1-2-phase W1-2-phase 2W1-2-phase A-Phase Current 100% 100% 100% 100% B-Phase Current
-100%
0% 0% 0%
4. Decay Mode Settings
It takes approximately four OSC cycles for discharging a current in PWM mode. The 25% decay mode is created by inducing decay during the last cycle in Fast Decay mode; the 50% Decay mode is created by inducing decay during the last two cycles in Fast Decay mode; and the 100% Decay mode is created by inducing decay during all four cycles in Fast Decay mode. Since the DCY1 and DCY2 pins have internal pull-down resistors, the Normal mode is selected when DCY1 and DCY2 are undriven.
DCY2 L L H H DCY1 L H L H Current Decay Setting Normal 0% 25% Decay 50% Decay 100% Decay
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5. Torque Settings (Current Value)
The ratio of the current necessary for actual operations to the predefined current adjusted by an external resistor can be selected as follows. The Weak Excitation mode should be selected to set a torque extremely low like when the motor is at a fixed position. Since the TQ2 and TQ1 pins have pull-down resistors, the 100% torque setting is selected when TQ2 and TQ1 are undriven.
TQ2 L L H H TQ1 L H L H Current Ratio 100% 75% 50% 20% (Weak excitation)
6. Calculation of the Predefined Output Current
To perform a constant current drive, the reference current should be adjusted by an external resistor. A charging stops when the NFA (NFB) voltage reaches 0.5 V (when the torque setting is 100%) so that a current does not exceed the predefined level. IOUT (A) = 0.5 (V)/RNF () Example: To set the peak current to 1 A, the value of an external resistor should be 0.5 .
7. Protect and MO Output Pins
These are open-drain outputs. An external pull-up resistor should be added to these pins when in use. If the TSD circuit is activated, Protect is driven Low. When the IC enters the Initial state, MO is driven Low.
Pin State Low High-Z Protect Thermal shutdown Normal operation MO Initial state Other than the initial state Open-drain connection
8. Adjusting the External Capacitor Value (COSC) and Minimum Clock Pulse Width (tW(CLK))
A triangular-wave is generated internally by CR oscillation. The capacitor is externally connected to the OSC pin. The recommended capacitor value is between 100 pF and 1000 pF. Approximate equation: fOSC = 1/{ COSC x 1.5 x (10/ COSC + 1)/66} x 1000 kHz (Since this is an approximation formula, the calculation result may not be exactly equal to the actual value.) The approximate values are shown below. The minimum clock pulse width (tW(CLK)) corresponds to the external capacitor (COSC ) as follows:
Capacitor 1000 pF 330 pF 100 pF Oscillating Frequency 44 kHz 130 kHz 400 kHz Minimum Clock Pulse Width tW(CLK) (Note 1) 90 s (Note 2) 30 s 10 s (Note 2)
Note 1: When the frequency of an input clock signal is high, the COSC value should be small so that the duty cycle of an input clock pulse does not become extremely high (should be around 50% or lower). Note 2: Not tested in production.
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Relationship Between the Enable and RESET Inputs and Output Signals
Example 1: ENABLE input in 1-2-phase excitation mode (M1: H, M2: L)
CW CLK ENABLE RESET MO voltage (%) 100 71
IA (current from 0 OUT_AP to OUT_AM)
-71 -100
t0
t1
t2
t3
OFF
t7
t8
t9
t10
t11
t12
Setting the ENABLE signal Low disables only the output signals, while internal circuitry other than the output block continues to operate in accordance with the CLK input. Therefore, when the ENABLE signal goes High again, the output current generation is restarted as if phases proceeded with the CLK signal.
Example 2: RESET input in 1-2-phase excitation mode (M1: H, M2: L)
CW CLK ENABLE RESET MO voltage (%) 100 71 IA (current from OUT_AP to OUT_AM) 0
-71 -100
t0
t1
t2
t3
t2
t3
t4
t5
t6
t7
t8
Setting the RESET signal Low causes the outputs to be put in the Initial state and the MO output to be driven Low (Initial state: A-channel output current is at its peak (100%)). When the RESET signal goes High again, the output current generation is restarted at the next rising edge of CLK with the state following the Initial state.
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2-Phase Excitation (M1: L, M2: L, CW Mode)
CW CLK MO (%) 100 IA 0
-100
(%) 100 IB 0
-100
t0
t1
t2
t3
t4
t5
t6
t7
1-2-Phase Excitation (M1: H, M2: L, CW Mode)
CW CLK MO (%) 100 71 IA 0
-71 -100
(%) 100 71 IB 0
-71 -100
t0
t1
t2
t3
t4
t5
t6
t7
t8
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4W1-2-Phase Excitation (M1: L, M2: H, CW Mode)
[%] 100 98 96 92 88 83 77 71 63 56 47 38 29 20 10 A-phase B-phase
0
-10 -20 -29 -38 -47 -56 -63 -71 -77 -83 -88 -92 -96 -98 -100
STEP
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2W1-2-Phase Excitation (M1: H, M2: H, CW Mode)
CW CLK MO (%) 100 98 92 83 71 56 38 20 IA 0
-20 -38 -56 -71 -83 -92 -98 -100
(%) 100 98 92 83 71 56 38 20 IB 0
-20 -38 -56 -71 -83 -92 -98 -100
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32
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CK
MO
M1 M2
RESET
(%) 100 91 71.4 40
IA
0
-40 -71.4 -91 -100
1-2-phase excitation
Other excitation
It is recommended that the state of the M1 and M2 pins be changed after setting the RESET signal Low during the Initial state (MO = Low). Even when the MO signal is Low, changing the M1 and M2 signals without setting the RESET signal Low may cause a discontinuity in the current waveform.
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9. Current Waveforms and Mixed Decay Mode Settings
The current decay rate of the Decay mode operation can be determined by the DCY1 and DCY2 inputs for constant-current control. The "NF" refers to the point at which the output current reaches its predefined current level, and the "RNF" refers to the monitoring timing of the predefined current. The smaller the MDT value, the smaller the current ripple amplitude. However, the current decay rate decreases.
fchop OSC Pin Internal Waveform Predefined Current Level Normal Mode NF RNF
Charge mode NF: Predefined current level Slow mode Current monitoring (When predefined current level > Output current) Charge mode
Predefined Current Level 25% Decay Mode NF
MDT Charge mode NF: Predefined current level Slow mode Mixed decay timing Fast mode Current monitoring (When predefined current level > Output current) Charge mode
RNF
Predefined Current Level 50% Decay Mode NF
MDT Charge mode NF: Predefined current level Slow mode Mixed decay timing Fast mode Current monitoring (When predefined current level > Output current) Charge mode
RNF
Predefined Current Level 100% Decay Mode NF
Charge mode NF: Predefined current level Fast mode Current monitoring (When predefined current level > Output current) Charge mode RNF
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10. Current Control Modes (Effects of Decay Modes)
* Increasing the current (sine wave)
Slow Predefined Current Level Fast Slow Predefined Current Level Charge Fast Slow Charge Fast Slow Charge
Fast
Charge
*
Decreasing the current with a high decay rate (The current decay rate in Mixed Decay mode is the ratio between the time in Fast-Decay mode (discharge time after MDT) and the remainder of the period.)
Slow Slow Charge Charge Since the current decays quickly, it can be decreased to the predefined value in a short time. Fast
Predefined Current Level
Fast Slow Predefined Current Level Slow
Fast
Charge
Fast
*
Decreasing the current with a low decay rate (The current decay rate in Mixed Decay mode is the ratio between the time in Fast-Decay mode (discharge time after MDT) and the remainder of the period.)
Since the current decays slowly, decreasing the current to the predefined value takes a long time (or the current cannot be properly decreased to the predefined value). Slow Slow Fast Charge Charge Fast
Predefined Current Level
Slow Fast
Slow Fast
Predefined Current Level
During Mixed Decay and Fast Decay modes, if the predefined current level is less than the output current at the RNF (current monitoring point), the Charge mode in the next chopping cycle will disappear (though the current control mode is briefly switched to Charge mode in actual operations for current sensing) and the current is controlled in Slow and Fast Decay modes (mode switching from Slow Decay mode to Fast Decay mode at the MDT point). Note: The above figures are rough illustration of the output current. In actual current waveforms, transient response curves can be observed.
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11. Current Waveforms in Mixed Decay Mode
fchop OSC Pin Internal Waveform fchop
IOUT Predefined Current Level
Predefined Current Level NF
NF
25% Mixed Decay Mode
RNF MDT (Mixed Decay Timing) Points
*
When the NF points come after Mixed Decay Timing points
Switches to Fast mode after Charge mode fchop fchop Predefined Current Level MDT (Mixed Decay Timing) Points NF RNF NF
IOUT
Predefined Current Level 25% Mixed Decay Mode
RNF
CLK Signal Input
*
When the output current value > predefined current level in Mixed Decay mode
fchop Predefined Current Level IOUT NF
fchop
fchop
RNF Predefined Current Level
NF
RNF
25% Mixed Decay Mode
MDT (Mixed Decay Timing) Points
CLK Signal Input
*: Even if the output current rises above the predefined current at the RNF point, the current control mode is briefly switched to Charge mode for current sensing.
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12. Current Waveform in Fast Decay Mode
After the output current to the load reaches the current value specified by RNF, torque or other means, the output current to the load will be fed back to the power supply fully in Fast Decay mode.
fchop Predefined Current Level IOUT
Switches to Charge mode briefly
Fast Decay Mode (100% Decay Mode)
RNF
Predefined Current Level
NF
RNF Since the predefined current level > output current, current control mode is switched from Charge mode NF Fast Decay mode even in the next chopping cycle. RNF
CLK Signal Input
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13. CLK and Internal OSC Signals and Output Current Waveform (when the CLK signal is asserted during Slow Decay mode)
25% Mixed Decay Mode fchop fchop OSC Pin Internal Waveform fchop
Predefined Current Level IOUT
NF MDT
NF Predefined Current Level RNF
MDT
RNF
CLK Signal Input The CR counter is reset here.
Switches to Charge mode briefly
When the CLK signal is asserted, the Chopping Counter (OSC Counter) is forced to reset at the next rising edge of the OSC signal. As a result, the response to input data is faster compared to methods in which the counter is not reset. The delay time that is theoretically determined by the logic circuit is one OSC cycle = 10 s at a 100-kHz chopping rate. After the OSC Counter is reset by the CLK signal input, the current control mode is invariably switched to Charge mode briefly for current sensing. Note: Even in Fast Decay mode, the current control mode is invariably switched to Charge mode briefly for current sensing.
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14. CLK and Internal OSC Signals and Output Current Waveform (when the CLK signal is asserted during Charge mode)
25% Mixed Decay Mode fchop fchop OSC Pin Internal Waveform fchop
Predefined Current Level MDT
NF Predefined Current Level IOUT RNF MDT
RNF
CLK Signal Input
Switches to Charge mode briefly The OSC Counter is reset here.
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15. CLK and Internal OSC Signals and Output Current Waveform (when the CLK signal is asserted during Fast Decay mode)
25% Mixed Decay Mode fchop fchop OSC Pin Internal Waveform fchop
Predefined Current Level IOUT
NF
MDT
Predefined Current Level
NF MDT
RNF
RNF
CLK Signal Input
Switches to Charge mode briefly The OSC Counter is reset here.
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16. Internal OSC Signal and Output Current Waveform when Predefined Current is Changed from Positive to Negative (when the CLK signal is input using 2-phase excitation)
25% Mixed Decay Mode fchop fchop fchop
Predefined Current Level IOUT
0
RNF RNF Predefined Current Level
MDT
NF
NF
CLK Signal Input The OSC Counter is reset here.
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Current Discharge Path when ENABLE is Set as Low During Operation
When all the output transistors are forced off during Slow Decay mode, the coil energy is discharged in the following modes: Note: Parasitic diodes are located on dotted lines. However, they are not normally used in normal Mixed Decay mode.
VM VM VM
U1 ON Note
U2 OFF
U1 OFF Note
U2 OFF
U1 OFF Note
U2 OFF
Load OFF L1 ON L2 ON L1
Load
ENABLE is set as low L2 ON L1 OFF
Load L2 OFF
RNF PGND
RNF PGND
RNF PGND
Charge Mode
Slow Mode
Forced OFF Mode
As shown in the figure above, output transistors have parasitic diodes. Normally, when the energy of the coil is discharged, each transistor is turned on allowing the current to flow in the reverse direction to that in normal operation; as a result, the parasitic diodes are not used. However, when all the output transistors are forced off, the coil energy is discharged via the parasitic diodes.
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Output Transistor Operating Modes
VM VM VM
U1 ON Note
U2 OFF
U1 OFF Note
U2 OFF
U1 OFF Note
U2 ON
Load OFF L1 ON L2 ON L1
Load L2 ON L1 ON
Load L2 OFF
RNF PGND
RNF PGND
RNF PGND
Charge Mode
Slow Mode
Fast Mode
Output Transistor Operating Modes
CLK Charge Slow Decay Fast Decay U1 ON OFF OFF U2 OFF OFF ON L1 OFF ON ON L2 ON ON OFF
Note: This table shows an example of when the current flows as indicated by the arrows in the above figures. If the current flows in the opposite direction, refer to the following table:
CLK Charge Slow Decay Fast Decay U1 OFF OFF ON U2 ON OFF OFF L1 ON ON OFF L2 OFF ON ON
Upon transitions of above-mentioned modes, a dead time of about 300 ns is inserted between each mode respectively.
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Test Points for AC Specifications
CLK
tCLK
tCLK
tpLH VM 90% 50% 10% tr tf tpHL 90% 50% 10%
GND
Figure 1 Timing Waveforms and Symbols
OSC-Charge DELAY: The OSC waveform is converted into the internal OSC waveform by checking the level of a chopping wave. The internal OSC signal is designed to be logic High when the OSC voltage is at 2 V or above, and to be logic Low when the OSC voltage is at 0.5 V or below. However, there is a response delay and that there occurs a peak-to-peak voltage variation.
2V OSC Waveform 0.5 V OSC Pin Internal Waveform
Figure 2 Timing Waveforms (OSC Signal)
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Power Dissipation
TB6560AHQ
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1. Power-on Sequence with Control Input Signals
Turn on VDD. Then, when the VDD voltage has stabilized, turn on VMA/B. Hold the control input pins Low while turning on VDD and VMA/B. (All the control input pins are internally pulled down.) After VDD and VMA/B completely stabilizes at the rated voltages, the RESET and ENABLE pins can be set High. If this sequence is not properly followed, the IC may not operate correctly, or the IC and the peripheral parts may be damaged. When RESET is released High, the CLK signal is applied and excitation is started. Only after ENABLE is also set High, outputs are enabled. When only RESET is set High, outputs are disabled and only the internal counter advances. Likewise, when only ENABLE is set High, the excitation will not be performed even if the CLK signal is applied and the outputs will remain in the initial state. An example of a control input sequence is shown below. A power-off sequence should be the reverse of this sequence.
CLK
RESET
H L H L H L
ENABLE
OUT
Z
Output
Internal current setting
Output current setting
Z Internal current setting: Disabled; Output OFF Internal current setting: Enabled
2. Power Dissipation
The power dissipation of the IC can be calculated by the following equation: P = VDD x IDD + IOUT x Ron x 2 drivers The higher the ambient temperature, the smaller the power dissipation. Examine the PD-Ta characteristic curve to determine if there is a sufficient margin in the thermal design.
3. Treatment of Heat-Radiating Fin
The heat-radiating fin pins of the TB6560AHQ/AFG (backside) are electrically connected to the backside of the die. Thus, if a current flows to the fin, the IC may malfunction. If there is any possibility of a voltage being generated between grounds and the fin, the fin pins should either be connected to ground or insulated.
4. Thermal Shutdown (TSD)
When the die temperature reaches 170C (typ.), the thermal shutdown circuit is tripped, switching the outputs to off. There is a variation of about 20C in the temperature at which the thermal shutdown circuit is tripped.
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Application Circuit Example
Fuse
5V
10 F
1 F
47 F
1 F
24 V
CLK
VDD
VMA
VMB OUT_AP H-SW A OUT_AM
RESET
ENABLE M1 NFCompA M2 Logic
PWM control circuit OUT_BP H-SW B OUT_BM
M
MCU or External input
CW/CCW DCY1 DCY2 TQ1 TQ2 Protect MO R1 R2 OSC 100 pF 400 kHz - SGND Current control
PWM control circuit NFCompB
NFA RNFA
NFB RNFB PGND 0.5 : IOUT (max) = 1.0 A
Note: Capacitors for the power supply lines should be connected as close to the IC as possible. Usage Considerations * A large current might abruptly flow through the IC in case of a short-circuit across its outputs, a short-circuit to power supply or a short-circuit to ground, leading to a damage of the IC. Also, the IC or peripheral parts may be permanently damaged or emit smoke or fire resulting in injury especially if a power supply pin (VDD, VMA, VMB) or an output pin (OUT_AP, OUT_AM, OUT_BP, OUT_BM) is short-circuited to adjacent or any other pins. These possibilities should be fully considered in the design of the output, VDD, VM, and ground lines. * A fuse should be connected to the power supply line. The rated maximum current of the TB6560AHQ is 3.5 A/phase and that of the TB6560AFG is 2.5 A/phase. Considering those maximum ratings, an appropriate fuse must be selected depending on operating conditions of a motor to be used. Toshiba recommends that a fast-blow fuse be used. * The power-on sequence described on page 28 must be properly followed. * If a voltage outside the operating range specified on page 6 (4.5 VDD 5.5, 4.5 VMA/B 34, VDD VMA/B) is applied, the IC may not operate properly or the IC and peripheral parts may be permanently damaged. Ensure that the voltage range does not exceed the upper and lower limits of the specified range.
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Package Dimensions
Weight: 9.86 g (typ.)
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Package Dimensions
Weight: 0.26 g (typ.) Note: The size of a backside heatsink is 5.5 mm x 5.5 mm. (Preliminary)
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Notes on Contents
1. Block Diagrams
Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes.
2. Equivalent Circuits
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes.
3. Timing Charts
Timing charts may be simplified for explanatory purposes.
4. Application Circuits
The application circuits shown in this document are provided for reference purposes only. Thorough evaluation is required, especially at the mass production design stage. Toshiba does not grant any license to any industrial property rights by providing these examples of application circuits.
5. Test Circuits
Components in the test circuits are used only to obtain and confirm the device characteristics. These components and circuits are not guaranteed to prevent malfunction or failure from occurring in the application equipment.
IC Usage Considerations
Notes on Handling of ICs
(1) The absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. Do not exceed any of these ratings. Exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. Use an appropriate power supply fuse to ensure that a large current does not continuously flow in case of over current and/or IC failure. The IC will fully break down when used under conditions that exceed its absolute maximum ratings, when the wiring is routed improperly or when an abnormal pulse noise occurs from the wiring or load, causing a large current to continuously flow and the breakdown can lead smoke or ignition. To minimize the effects of the flow of a large current in case of breakdown, appropriate settings, such as fuse capacity, fusing time and insertion circuit location, are required. If your design includes an inductive load such as a motor coil, incorporate a protection circuit into the design to prevent device malfunction or breakdown caused by the current resulting from the inrush current at power ON or the negative current resulting from the back electromotive force at power OFF. IC breakdown may cause injury, smoke or ignition. Use a stable power supply with ICs with built-in protection functions. If the power supply is unstable, the protection function may not operate, causing IC breakdown. IC breakdown may cause injury, smoke or ignition. Do not insert devices in the wrong orientation or incorrectly. Make sure that the positive and negative terminals of power supplies are connected properly. Otherwise, the current or power consumption may exceed the absolute maximum rating, and exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. In addition, do not use any device that is applied the current with inserting in the wrong orientation or incorrectly even just one time.
(2)
(3)
(4)
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Points to Remember on Handling of ICs
(1) Thermal Shutdown Circuit Thermal shutdown circuits do not necessarily protect ICs under all circumstances. If the thermal shutdown circuits operate against the over temperature, clear the heat generation status immediately. Depending on the method of use and usage conditions, such as exceeding absolute maximum ratings can cause the thermal shutdown circuit to not operate properly or IC breakdown before operation. Heat Radiation Design In using an IC with large current flow such as power amp, regulator or driver, please design the device so that heat is appropriately radiated, not to exceed the specified junction temperature (TJ) at any time and condition. These ICs generate heat even during normal use. An inadequate IC heat radiation design can lead to decrease in IC life, deterioration of IC characteristics or IC breakdown. In addition, please design the device taking into considerate the effect of IC heat radiation with peripheral components. Back-EMF When a motor rotates in the reverse direction, stops or slows down abruptly, a current flow back to the motor's power supply due to the effect of back-EMF. If the current sink capability of the power supply is small, the device's motor power supply and output pins might be exposed to conditions beyond maximum ratings. To avoid this problem, take the effect of back-EMF into consideration in system design. Short-Circuits The IC may be permanently damaged in case of a short-circuit across its outputs, a short-circuit to power supply or a short-circuit to ground. These possibilities should be fully considered in the design of the output, VDD, VM and ground lines. Short-Circuits between Adjacent Pins in the TB6560AHQ In the TB6560AHQ, the term "adjacent pin" includes a pin diagonally closest to a given pin. For example, pin 3 has four adjacent pins: 1, 2, 4 and 5. Depending on the specified voltage and current, a large current might abruptly flow through the TB6560AHQ in case of a short-circuit between any adjacent pins that are listed below. If the large current persists, it may lead to a smoke emission. 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) 11) 12) 13) 14) 15) 16) 17) 18) 19) Pins 7 and 8 Pins 7 and 9 Pins 8 and 9 Pins 9 and 10 Pins 9 and 11 Pins 10 and 12 Pins 11 and 12 Pins 11 and 13 Pins 12 and 13 Pins 12 and 14 Pins 13 and 14 Pins 13 and 15 Pins 14 and 16 Pins 15 and 16 Pins 16 and 17 Pins 16 and 18 Pins 17 and 18 Pins 18 and 19 Pins 18 and 20
(2)
(3)
(4)
(5)
Therefore, to avoid a continuous overcurrent due to the above-described short-circuit and allow the TB6560AHQ/AFG to be fail-safe, an appropriate fuse should be added at the right place, or overcurrent shutdown circuitry should be added to the power supply. The rated current of a fuse may vary depending on actual applications and its characteristics. Thus, an appropriate fuse must be selected experimentally.
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About solderability, following conditions were confirmed * Solderability (1) Use of Sn-37Pb solder Bath * solder bath temperature = 230C * dipping time = 5 seconds * the number of times = once * use of R-type flux (2) Use of Sn-3.0Ag-0.5Cu solder Bath * solder bath temperature = 245C * dipping time = 5 seconds * the number of times = once * use of R-type flux
RESTRICTIONS ON PRODUCT USE
* The information contained herein is subject to change without notice. 021023_D
070122EBA_R6
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 070122_C * Please use this product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. 060819_AF * The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E
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